The present invention relates to a fuse and a fuse latch circuit, and more particularly to a layout of these fuses and fuse latch circuits.
FIG. 1 is a layout of conventional fuses and fuse latch circuits. FIG. 1 shows an example of a fuse and a fuse latch circuit, used for a redundancy circuit in semiconductor memory.
As shown in FIG. 1, the conventional fuses (FUSE) and fuse latch circuits (FUSE LAT.), which correspond one to one to the fuses, are disposed in a fuse area 101 and a fuse latch circuit area 102, which are adjacent to each other on a chip.
Basic patterns 103 and 104 are available to dispose fuses and fuse latch circuits, respectively. In the fuse area 101 and fuse latch circuit area 102, these basic patterns 103 and 104 are repeated a predetermined number of times to lay out a predetermined number of fuses and fuse latch circuits on a chip.
A repetition pitch P2 between the basic patterns 104 of the conventional fuse latch circuits is equal to a repeating pitch P1 between the basic patterns 103 of the conventional fuses. This is because equalizing the repetition pitches P2 and P1 helps connect the fuses with the fuse latch circuits, corresponding to the fuses.
In the fuse latch area 102, some basic patterns 104 can be repeatedly used for each fuse latch circuit; others are not. For example, for the fuse latch circuits used for a redundancy circuit, which are in FIG. 1, repeatable basic patterns 104 are common to a plurality of addresses, and unrepeatable patterns are for local address signal lines 105. The local address signal lines 105 connect global address signal lines disposed, for example, in the direction of repeated basic patterns 104 with the fuse latch circuits.
Different addresses could be entered for different fuse latch circuits. Because of this, a hierarchy in which a pattern of local address signal lines 105 is laid out differs from a hierarchy in which a pattern common to a plurality of addresses. Here the term "hierarchy" does not mean a "physically upper or lower level." For example, in semiconductor memory, a plurality of the same layouts are provided. Thus in a layout block (cell), another layout block is frequently disposed. Such a structure is called a "hierarchy" in a layout.
Each local address signal line 105 differs from a basic pattern 104 of fuse latch circuits in terms of hierarchy but is laid out where the basic pattern 104 is disposed.
However, such a layout increases the number of local address signal lines 105. As a result, the total parasitic capacitance of address signal lines, including global address lines, increases, thus markedly delaying address signal transmission.
To solve this problem, a semiconductor memory device is adapted so that the number of local address signal lines 105 is reduced by disposing a plurality of fuse latch circuits corresponding to the same address in a group and making the local address signal lines 105 common to the plurality of fuse latch circuits to reduce the total parasitic capacitance of address signal lines, as shown in FIG. 2 (Jpn. Pat. Appln. KOKAI Publication No. 11-135754).
However, at any rate, a local address signal line 105 differs from a basic pattern 104 of fuse latch circuits in terms of hierarchy but is laid out where the basic pattern 104 is disposed. This requires that the basic pattern 104 of fuse latch circuits is provided with a space (or an area) 106 in which local address signal lines are disposed. Because wiring in the same wiring layer as the local address signal lines 105 cannot be installed in the space, layout is restricted.
Such a restriction limits the flexibility of layout and prevents area in which fuse latch circuits are disposed from being reduced, and moreover, increases unnecessary area.
The basic pattern 104 of fuse latch circuits is repeated in a conventional fuse latch area 102 so that the patterns are close to each other, patterns which do not necessarily need to be repeated at the pitch P2 are repeated.
Such patterns are contacts to a semiconductor substrate or a well.
Also because patterns which do not necessarily need to be repeated at the pitch P2 are repeated than necessary, fuse latch circuit area reduction is prevented, or fuse latch circuit area even increases.